Multi-gigabit per second (Gbps) communication between various chips on a circuit board or modules on a backplane has been in use for quite a while. Data transmission is usually from a transmitter that serializes parallel data for transmission over a communication media, such as twisted pair conductors as a cable or embedded in a backplane, fiber optic cable, or coaxial cable(s), to a receiver that recovers the transmitted data and deserializes the data into parallel form. However, data transmission greater than 10 Gbps over communication paths longer than a few centimeters has been difficult to achieve because various signal impairments, such as intersymbol interference (ISI), crosstalk, echo, and other noise, can corrupt the received data signal to such an extent that a receiver unable to recover the transmitted data at the desired high data rate with an acceptable level of error performance.
Various techniques are employed to improve the performance of the receiver. One technique is to provide the receiver with an analog front end (AFE) having linear and decision feedback equalizers to compensate for high, frequency-dependent insertion losses of the media. Even though the shape of the received signal is improved by the AFE, the signal-to-noise ratio (SNR) of the received signal might not be high enough for acceptably low error rate detection because the received signal is subject to noise that the AFE cannot fully correct.
One way to improve the SNR of the received signal is for the transmitter to drive the media with signals of sufficient amplitude that the received signal has sufficient amplitude relative to the amplitude of the noise on the received signal such that the receiver properly recovers the transmitted data from the received signal. Correspondingly, the transmitter can send the data in a way that simply reduces the amount of noise on the signal as received by the receiver. Through the use of shielding the media and by using differential signaling over balanced media such as shielded twisted pair, the media itself is less susceptible to interference, resulting in lower noise in the received signal and, consequently, a higher SNR in the signal presented to the receiver.
As transmission data rates increase, the speed (bandwidth) of the transistors used in the transmitter must also increase. For a given CMOS technology, thin-oxide transistors offer higher speed than thick-oxide transistors. Concomitant with the increase in speed, the voltage level handling capability of transistors decreases. It is well known that the maximum achievable peak-to-peak output swing of a differential voltage mode driver is limited to the power supply voltage utilized by the driver under impedance-matched conditions. Operating the transistors at voltage levels needed to deliver high-amplitude output signals can overstress the transistors, causing them to fail. Thus, a transmitter requiring higher speed transistors to transmit signals at a desired data rate without damaging the transistors might result in the signal presented to the receiver having an SNR insufficient for acceptably low error rate communication.
Therefore, it is desirable to provide a transmitter capable of utilizing high-speed transistors to transmit data at high data rates and also capable of producing output signals of sufficient amplitude for reliable communication at the high data rates without overstressing the transistors.